Computer systems of the PC type usually employ a so-called expansion bus to handle various data transfers and transactions related to I/O and disk access. The expansion bus is separate from the system bus or from the bus to which the processor is connected, but is coupled to the system bus by a bridge circuit.
For some time, all PC's employed the ISA (Industry Standard Architecture) expansion bus, which was an 8-Mhz, 16-bit device (actually clocked at 8.33 Mhz). Using two cycles of the bus clock to complete a transfer, the theoretical maximum transfer rate was 8.33 Mbytes/sec. Next, the EISA (Extension to ISA) bus was widely used, this being a 32-bit bus clocked at 8-Mhz, allowing burst transfers at one per clock cycle, so the theoretical maximum was increased to 33 Mbytes/sec. As performance requirements increased, with faster processors and memory, and increased video bandwidth needs, a high performance bus standard was a necessity. Several standards were proposed, including a Micro Channel architecture which was a 10-Mhz, 32-bit bus, allowing 40 MByte/sec, as well as an enhanced Micro Channel using a 64-bit data width and 64-bit data streaming, theoretically permitting 80-to-160 Mbyte/sec transfer. The requirements imposed by the use of video and graphics transfer on networks, however, necessitate even faster transfer rates. One approach was the VESA (Video Electronics Standards Association) bus which was a 33 Mhz, 32-bit local bus standard specifically for a 486 processor, providing a theoretical maximum transfer rate of 132 Mbyte/sec for burst, or 66 Mbyte/sec for non-burst; the 486 had limited burst transfer capability. The VESA bus was a short-term solution as higher-performance processors, e.g., the Intel P5 and P6 or Pentium and Pentium Pro processors, became the standard.
The PCI (Peripheral Component Interconnect) bus was proposed by Intel as a longer-term solution to the expansion bus standard, particularly to address the burst transfer issue. The original PCI bus standard has been upgraded several times, with the current standard being Revision 2.1, available from a trade association group referred to as PCI Special Interest Group, P.O. Box 14070, Portland, Oreg. 97214. The PCI Specification, Rev. 2.1, is incorporated herein by reference. Construction of computer systems using the PCI bus, and the PCI bus itself, are described in many publications, including "PCI System Architecture," 3rd Ed., by Shanley et al., published by Addison-Wesley Pub. Co., also incorporated herein by reference. The PCI bus provides for 32-bit or 64-bit transfers at 33- or 66-Mhz; it can be populated with adapters requiring fast access to each other and/or with system memory, and that can be accessed by the host processor at speeds approaching that of the processor's native bus speed. A 64-bit, 66-MHz PCI bus has a theoretical maximum transfer rate of 528 MByte/sec. All read and write transfers over the bus can be burst transfers. The length of the burst can be negotiated between initiator and target devices, and can be any length.
System and component manufacturers have implemented PCI bus interfaces in various ways. For example, Intel Corporation manufactures and sells a PCI Bridge device under the part number 82450GX, which is a single-chip host-to-PCI bridge, allowing CPU-to-PCI and PCI-to-CPU transactions, and permitting up to four P6 processors and two PCI bridges to be operated on a system bus. Another example, offered by VLSI Technology, Inc., is a PCI chipset under the part number VL82C59x SuperCore, providing logic for designing a Pentium based system that uses both PCI and ISA buses. The chipset includes a bridge between the host bus and the PCI bus, a bridge between the PCI bus and the ISA bus, and a PCI bus arbiter. Posted memory write buffers are provided in both bridges, and provision is made for Pentium's pipelined bus cycles and burst transactions.
The "Pentium Pro" processor, commercially available from Intel Corporation uses a processor bus structure as defined in the specification for this device, particularly as set forth in the publication "Pentium Pro Family Developer's Manual" Vols. 1-3, Intel Corp., 1996, available from McGraw-Hill, and incorporated herein by reference; this manual is also available from Intel by accessing &lt;http://www.intel.com&gt;.
A CPU operates at a much faster clock rate and data access rate than most of the resources it accesses via a bus. In earlier processors, such as those commonly available when the ISA bus and EISA bus were designed, this delay in reading data from a resource on the bus was handled by wait states. When a processor requested data that was not immediately available due to a slow memory or disk access, then the processor merely marked time using wait states, doing no useful work, until the data finally became available. In order to make use of this delay time, a processor such as the P6 provides a pipelined bus that allows multiple transactions to be pending on the bus at one time, rather than requiring one transaction to be finished before starting another. Also, the P6 bus allows split transactions, i.e., a request for data may be separated from the delivery of the data by other transactions on the bus. The P6 processor uses a technique referred to as a "deferred transaction" to accomplish the split on the bus. In a deferred transaction, a processor sends out a read request, for example, and the target sends back a "defer" response, meaning that the target will send the data onto the bus, on its own initiative, when the data becomes available. Another transaction available on the P6 bus is a "retry" response. If a target is not able to supply a requested item, the target may respond to the request from the processor using a retry signal, and in that case the processor will merely send the request again the next time it has access to the bus.
The PCI bus specification as set forth above does not provide for deferred transactions. There is no mechanism for issuing a "deferred transaction" signal, nor for generating the deferred data initiative. Accordingly, while a P6 processor can communicate with resources such as main memory that are on the processor bus itself using deferred transactions, this technique is not employed when communicating with disk drives, network resources, compatibility devices, etc., on an expansion bus.
In existing computer systems read and write transactions commonly run from an initiator on one bus to a target on another bus. These transactions commonly traverse through a bus-to-bus bridge which connects the two buses. A bus may contain a number of slots which may be filled by devices which are potential initiators or targets. A number of problems may arise which cause a particular bus to become inoperable. One common situation is for a bus hang condition to arise which may occur, for example, in the common IRDY bus hang situation. Once the bus recognizes an error condition, the transaction which gave rise to the error could be aborted. However, this may not always cure the problem.
Thus, it would be desirable to determine the cause of the problem and to attempt to overcome it if possible. This type of diagnostic procedure may be complicated by the fact that it is necessary to access the troubled bus in order to obtain information about the nature of the problem which has occurred. For example, devices which are on the bus may contain information about the transactions which occurred previously. This information may provide useful information for determining the source of the problem and perhaps even the nature of the problem. When the bus is inoperative, there may be no way for the internal system to determine how to correct itself. As a result, many error conditions result in system crashes. System crashes generally necessitate a visit from a repair technician and often entail considerable downtime for the entire system.
Another issue which arises in many current computer systems involves bridges which include devices which may be either initiators or targets of transactions being run on particular buses. Generally, a transaction passing through a bridge is run on a connected bus. Because of the way the buses operate, a signal is sent out on the bus to a target device but the signal also proceeds to the end of the bus and is reflected back. The signal that the target device receives is a combination of the initial wave and the reflected wave. As a result, the signal integrity of the received signals may be less for devices resident on the bridge itself, because those devices receive the reflected signal with the longest delay. As a result, the signal received by bridge resident targets may have integrity problems because of the considerable delay between receipt of the initial signal and the reflected signal.
There is a considerable need for a computer system which facilitates the correction of bus errors and which improves the integrity of bus signals.